The underlying technology and benefits of optical data transmission and fiber optic technology are well known in the art and beyond. Signals in the form of light, at wavelengths both within and beyond the visible spectrum, can be transmitted through free space, a reflective wave guide such as a fiber optic medium, or similar means. Whatever medium is used, the potential bandwidth is tremendous. Moreover, as compared to electrical signals transmitted through conventional conductive wiring, problems with noise, crosstalk, and similar concerns are reduced if not eliminated. It is no surprise, therefore, that fiber optic cabling has been replacing conventional conductive cabling as the backbone of public and private data networks.
Optical data transmission can be of tremendous potential benefit not only in transmitting data between computer systems, but within computer systems as well. Optical data transmission holds great promise for reducing or eliminating bottlenecks which limit computer processing throughput. With improvements in semiconductor miniaturization and manufacturing, today's microprocessors operate at gigahertz clock speeds, while other aspects of computer design and manufacture have not kept pace. As a result, a microprocessor may run at gigahertz speeds, but be left sitting idle waiting on the computer's subsystems to respond to instructions or return data.
To name one very significant example, the response time of computer memory systems has not at all kept up with increases in microprocessor speed. “Memory latency,” i.e., delays in responding to processor requests for data, is a large problem. Typical computer motherboards operate at between one hundred and three hundred megahertz, almost an order of magnitude slower than typical microprocessors. Moreover, the disparity between the speed of processor clocks and memory clocks is growing. Currently, the ratio of processor clock speed to memory clock speed typically is 8:1, but that ratio is predicted to increase to 100:1 in the next few years. Further compounding the problem is the fact that a memory system may require ten or more of its own memory clock cycles to respond to a memory retrieval request, thus, the ratio for a complete memory cycle is far worse. Today, completion of one full memory cycle may result in the waste of hundreds of processing cycles. In the near future, based on current performance trends in microprocessors, completion of a memory cycle may result in the waste of thousands of processing cycles.
Although memory latency results in part from the slower speed of memory chips themselves, an appreciable portion of this delay is because of the time required to route data from the system controller to memory modules, and within memory modules to the module's memory chips. Problems such as cross talk, skew, and similar concerns limit just how quickly data can be communicated through memory systems. In addition, while microprocessors can accommodate larger and larger data words and ranges of addresses, data and address busses have not increased commensurately. As a result, data and address signals bits must be multiplexed in order to transmit that information on existing busses, further impairing the exchange of data with memory.
Memory modules used in computer systems commonly are in the form of single in-line memory modules (“SIMMs”) and double in-line memory modules (“DIMMs”). An example of a conventional SIMM memory module 10 is shown in FIG. 1. The memory module 10 includes a circuit board substrate 14 on which several memory devices 20, typically dynamic random access memories (“DRAMs”), are mounted. Terminals 24 are formed along an edge of the substrate 14, which mate with slotted connectors (not shown ) typically mounted on a computer system mother-board. The terminals 24 are electrically coupled to the power and signal terminals on the memory devices 20. Also mounted on the substrate 14 may be a register 26 that stores command and address signals applied to the memory module 10 through the terminals 24 responsive to a clock signal that is also applied to the memory module 10 through the terminals 24. The register 26 then applies the command and address signals to the memory devices 20. Memory modules having a register 26 operating in this manner are known as “registered DRAM modules.” However, it should be understood that memory modules often do not include the register 26, and they may include components in addition to those shown in FIG. 1.
A portion of a memory system 30 shown in FIG. 2 includes three memory modules 10a, 10b, and 10c coupled to a system controller 32 though a common data bus 34, address bus 36 and command bus 38. The system controller 32 initiates a memory operation by coupling a memory request in the form of a memory command and a memory address (generally in the form of a row address and a column address) to all of the memory modules 10a, 10b, and 10c through the command bus 38 and the address bus 36, respectively. If the memory operation is a write operation, the system controller 32 will also couple write data to the memory modules 10a, 10b, and 10c through the data bus 34. To prevent all of the memory modules 10a, 10b, and 10c from responding to the memory request, the system controller 32 also generally applies a unique chip select or similar select signal to each of the memory modules 10a, 10b, and 10c. A unique select signal is thus applied to each of the memory modules 10a, 10b, and 10c so that only the desired memory module of modules 10a, 10b, and 10c responds to the memory request.
The bandwidth of data between the system controller 32 and the memory modules 10a, 10b, and 10c can be increased by simultaneously accessing the memory devices 20 (FIG. 1) in each of the modules 10a, 10b, and 10c. For example, the sixteen memory devices 20 included in the memory module 10a, 10b, and 10c may be divided into four sets or “ranks” of four memory devices. Data may be read from all four of the ranks responsive to a single memory read request so that data must be coupled through the data bus 34 at a rate that is four times faster than the rate at which data is coupled from each rank of the memory devices 20. However, as the operating speed of memory devices continues to increase, the bandwidth of data coupled from the memory modules 10a, 10b, and 10c may be limited by the bandwidth of the data bus 34 coupled between the system controller 32 and the memory modules 10a, 10b, and 10c. 
Another factor that limits the operating speed of computer systems using the system controller 32 coupled to the memory modules 10a, 10b, and 10c through the buses 34, 36, and 38 is the need to allow for a settling time between writing data to a memory module 10a, 10b, or 10c and reading data from a memory module 10. When the system controller 32 outputs data to the memory modules, the data signals are reflected from various locations, such as the junction between the data bus 34 and terminals 24 (FIG. 1) on the substrates 14 of the modules 10. Therefore, signal induced noise is present on the data bus for a considerable period after data have been written to the memory modules 10a, 10b, and 10c. Signal induced noise is generated on the data bus for the same reason in a read operation when one of the memory modules 10a, 10b, and 10c couples data onto the data bus 34 for transfer to the system controller 32. This noise must be allowed to dissipate before data are subsequently written to or read from the memory modules 10a, 10b, and 10c or else the noise may be mistakenly interpreted as read or write data. The need to provide for a settling time read can markedly reduce the effective memory bandwidth of computer systems and other devices using memory modules.
Not only is the communication between the system controller 32 (FIG. 2) and the memory modules 10a, 10b, and 10c a concern, but comparable concerns arise within the module 10 (FIG. 1) in communications between the register 26 and memory devices 20. A basic concern is that great care must be taken in manufacturing a substrate 14 which includes workable connections (not shown) between the register 26 and the memory devices 20. In addition, because of the signal currents passing along these necessarily closely disposed signal lines, phenomena such as noise and cross-talk could result in data communications errors between the register 26 and memory devices 20. Certainly, settling time must be allowed for intramodule communications just as it must for intermodule communications, further slowing the effective speed of the system memory.
Thus, both between and within memory modules, there is therefore a need for a memory system communications technique that permits a higher bandwidth of data transfer to and from memory modules and memory devices and that reduces or eliminates delays in writing data to and reading from memory in a computer system. It is to this objective that the present invention is directed.